Hipdn: a Power Distribution Network for Efficient On-chip Power Delivery and Fine- Grain Low-power Applications

While the semiconductor roadmap is about to locate in 16nm-FinFET (or Tri-Gate) era, power budget is being entitled major concern to contemporary electronics and future nanometer devices. In this work, a new Power Distribution Network (PDN), referred to as HiPDN, is disclosed for further fine-grain power saving and higher power integrity for supplies in multi-voltage domains. The proposed PDN employs two types of Integrated Voltage Regulators (IVR) with large difference in voltage regulation range. By combining the proposed PDN with the Adaptive Voltage Scaling (AVS) technique, voltage guard-bands can be mitigated to lower the safety margin for voltage variation, i.e., reducing DC set points, thereby effectively decreasing the overhead of power dissipation. In comparison to existing PDNs, theoretical results with a simple equivalent circuit model demonstrate an increase of power saving achieved by HiPDN, thus, allowing longer battery life. Finally, this work provides an on-chip power delivery methodology to improve power efficiency and a simple model to evaluate a PDN and its IVRs.